Lpm_mult mega function in modelsim, Help !!!!

Yes....., I converted to vhdl my design, and there is a component named mult (connected to input and output ports), this component has her own vhdl file named mult.vhd, inside this file is :

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY lpm;

USE lpm.all;

library work;

use work.pack.all;

ENTITY mult IS

PORT

(

dataa : IN STD_LOGIC_VECTOR (ancho_ext-1 DOWNTO 0);

datab : IN STD_LOGIC_VECTOR (ancho_ext-1 DOWNTO 0);

result : OUT STD_LOGIC_VECTOR ((ancho_ext*2)-1 DOWNTO 0)

);

END mult;

ARCHITECTURE SYN OF mult IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR ( (ancho_ext*2)-1 DOWNTO 0);

COMPONENT lpm_mult

GENERIC (

lpm_hint : STRING;

lpm_representation : STRING;

lpm_type : STRING;

lpm_widtha : NATURAL;

lpm_widthb : NATURAL;

lpm_widthp : NATURAL

);

PORT (

dataa : IN STD_LOGIC_VECTOR (ancho_ext-1 DOWNTO 0);

datab : IN STD_LOGIC_VECTOR (ancho_ext-1 DOWNTO 0);

result : OUT STD_LOGIC_VECTOR ((ancho_ext*2)-1 DOWNTO 0)

);

END COMPONENT;

BEGIN

result <= sub_wire0((ancho_ext*2)-1 DOWNTO 0);

lpm_mult_component : lpm_mult

GENERIC MAP (

lpm_hint => "MAXIMIZE_SPEED=5",

lpm_representation => "UNSIGNED",

lpm_type => "LPM_MULT",

lpm_widtha => ancho_ext,

lpm_widthb => ancho_ext,

lpm_widthp => ancho_ext*2

)

PORT MAP (

dataa => dataa,

datab => datab,

result => sub_wire0

);

END SYN;

We can see other component named lpm_mult.... the problem here is to find the vhdl file for this component and use it in modelsim.....

i think this is all that's required to simulate lpm functions:

--- Quote Start ---

The altera_mf_components.vhd and altera_mf.vhd model files should be compiled

into the altera_mf library. The 220pack.vhd and 220model.vhd model files should be

compiled into the lpm library.

--- Quote End ---

the files can be found in $QUARTUS_ROOTDIR/eda/sim_lib

reference: ModelSim Support section of QII Handbook, page 6:

http://www.altera.com/literature/hb/qts/qts_qii53001.pdf

You shoud use the verilog/VHDL file for the LPM_MULT and the Verilog/VHDL file for the whole design.

The last file can be created running File -> Create/Update -> HDL from current file.

Better to have everything in a single language (Verilog or VHDL).

I don't know if you also need Altera libraries.

Probably you don't need them for a functional simulation.