Forum Discussion
Altera_Forum
Honored Contributor
15 years agoYou shoud use the verilog/VHDL file for the LPM_MULT and the Verilog/VHDL file for the whole design.
The last file can be created running File -> Create/Update -> HDL from current file. Better to have everything in a single language (Verilog or VHDL). I don't know if you also need Altera libraries. Probably you don't need them for a functional simulation.