lpm functions and hdl

Hi ,

Yes and no :-) If you choose an LPM_ADDSUB the cost for the lpm function goes to 16+ LE's whereas the counter comes in as 8LE's + 8LUT's. So what's the best way to synthesize and up/down counter without +/-? Anyone know?

It's actually for a Cylcone II, so it's(IIRC) a 4-input LUT. Even with all (synchronous) functions enabled and an asynchronous reset, it comes down to 11 LE's and is listed in as 8LE's + 8 LUT's. I *kinda* need the q_next in order to get the answer before the next clock but if that makes a huge difference than that's 1 extra clock per instruction, which would kinda suck.. I'll give it a whirl though...

Did some more sleuthing and it's indeed the fact that you expose next_q. Without exposing next_q a synchronous, 8-bit loadable counter with asynchronous reset comes in at 9LE's, which is inline with the LPM function.

Unless you really need the resources, you should ALWAYS choose whichever option is easier for a fellow engineer (or yourself in 12 months time) to understand. Choosing an obscure "clever" option will never earn you brownie points with anyone.

The case shows that the synthesis tool is pretty good in optimizing arithmetic code so that functionally equivalent designs usually end up with equal resource usage.

We shouldn't question the OP's intentions: the OP may need the q_next to take some look-ahead decision.

module register8 (
            clk,
            clken,
            reset_n,
            data,
            load,
            cnt_en,
            updown,
            q,
            q_next
            );
input clk;
input clken;
input reset_n;
input  data;
input load;
input cnt_en;
input updown;
output  q, q_next;
reg  addsub;
always @(*)
    if ( updown )
        addsub =  - 8'd1;
    else
        addsub = 8'd1;
// asynchronous 'next' value. This is used extensively for flags 
reg  q, q_next;
always @(*)
    q_next = q + addsub;
always @(posedge clk or negedge reset_n )
    if ( !reset_n )
        q <= 8'd0;
    else if ( clken & (load | cnt_en))
        if (load )
            q <= data;
        else
            q <= q_next;
endmodule

module register8 (            clk,
            clken,
            reset_n,
            data,
            load,
            cnt_en,
            updown,
            q,
            q_next
            );
input clk;
input clken;
input reset_n;
input  data;
input load;
input cnt_en;
input updown;
output  q, q_next;
reg  addsub;
always @(*)
    if ( updown )
        addsub =  - 8'd1;
    else
        addsub = 8'd1;
// asynchronous 'next' value. This is used extensively for flags 
reg  q, q_next;
always @(*)
    if (load)
        q_next = data;
    else
        q_next = q + addsub;
always @(posedge clk or negedge reset_n )
    if ( !reset_n )
        q <= 8'd0;
    else if ( clken & cnt_en)
        q <= q_next;
endmodule

module register8 (            clk,
            clken,
            reset_n,
            data,
            load,
            cnt_en,
            updown,
            q,
            q_next
            );
input clk;
input clken;
input reset_n;
input  data;
input load;
input cnt_en;
input updown;
output  q, q_next;
reg  addsub;
always @(*)
    if ( cnt_en)
        if (updown )
            addsub =  - 8'd1;
        else
            addsub = 8'd1;
    else
        addsub = 0;
// asynchronous 'next' value. This is used extensively for flags 
reg  q, q_next;
always @(*)
    if (load)
        q_next = data;
    else
        q_next = q + addsub;
always @(posedge clk or negedge reset_n )
    if ( !reset_n )
        q <= 8'd0;
    else if ( clken )
        q <= q_next;
endmodule

Thanks guys!

always @(posedge clk or negedge reset_n )
  if (!reset_n)
    q <= 8'd0;
  else if (clken)
  begin
    if (load)
      q <= data;
    else if (cnt_en)
    begin
      if (updown)
        q <= q - 1;
      else 
        q <= q + 1;
    end
  end