Frank,
Again it is not up to us to question the OP's intention: if the OP wants a q_next, so we should give him that, no? I think the OP is now painfully aware that there is a
cost for this q_next option.
My third solution is indeed functionally equivalent to the OP's original post# 1. The difference is in the coding: I'm sure you can spot the difference, studying the RTL diagrams will help, I attach the RTL schematic for the original post.
https://www.alteraforum.com/forum/attachment.php?attachmentid=14930 I tried to put everything in 2 always blocks, one combinatorial, the other sequential, but that didn't work. I normally don't do Verilog, so I didn't persist.
Regards,
Josy