lpm_ff megafunction

I am analyzing an old design of an FPGA that looks like it is clocking data in with the lpmFF megafunction set up as a D flip flop. But looking at the input data with an analyzer, the input data goes valid after the rising edge of the clock input to the megawizard flip flop so it seems like a D flip flop would not work properly. Typically a D flipflop sets the output to the input on the rising edge of the input clock. Just wondering if there is a way to set up the lpm_FF megafunction to have the output follow the input when the clock signal is high and then latch the output when clock goes low as perhaps this is what is going on? Also is there a way to simulate what the design will do by entering simulated input signals?