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Honored Contributor
Honored Contributorlpm_ff megafunction
I am analyzing an old design of an FPGA that looks like it is clocking data in with the lpmFF megafunction set up as a D flip flop. But looking at the input data with an analyzer, the input data goe...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Looks like the previous timing diagram got messed up, I have included a txt file showing input signals to the megawizard, thanks. --- Quote End --- The diagram you give shows the '1' value of data is more a glitch than a real data value, and is rightly ignored. pletz has given you a diagram of what should really happen.
