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Honored Contributor
Honored Contributorlpm_ff megafunction
I am analyzing an old design of an FPGA that looks like it is clocking data in with the lpmFF megafunction set up as a D flip flop. But looking at the input data with an analyzer, the input data goe...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Looks like the previous timing diagram got messed up, I have included a txt file showing input signals to the megawizard, thanks. --- Quote End --- Hi, you have to keep the required timing conditions in order to get the right functionality. The input data needs to stable a certain time before the active edge ( setup requirement) and needs to stable for a ceratin time after the active edge ( hold time requirement). The output of your FF will be always "0" with the given timing diagramm. Have a look to the attached file. Kind regards GPK
