Forum Discussion
Altera_Forum
Honored Contributor
13 years agoWas able to pass timing for now. It seems the only way to achieve positive slack is to keep adding latency cycles. I finally went for broke and set the core to its max latency (64 cycles for a 64-bit numerator) and was able to get the slack up to +0.200. Going to start scaling back a little to see the minimum I can use.
Also, I found it interesting that when I created a project with 2 input convert to float cores, a floating point divide core, and an output convert float to fixed core, all those cores together were about 20-25% of the registers used in a single fixed point 64-bit divide. Thanks all for your replies.