Forum Discussion
Altera_Forum
Honored Contributor
13 years agodivide involves many levels of logics. besides, you are using quite a high frequency clock. the most effective way is to increase latency of your divide to meet timing closure. Increasing latency means it reduces the logics that a datapath needs to go through from one register to another register. If your system is processing data in parallel, increasing latency shouldn't affect performance much as it only adds some overheads before you get the outputs.