Honored Contributor
Honored ContributorI'm hesitant to implement this type of method for a couple reasons. The first being that I'm relatively new to VHDL design and would feel more comfortable using Altera's generated core rather than trying to create my own using this complex method. I'm also real scarce on resources in the FPGA as it is.
The processor design is for the most part complete. My only remaining hurdle is trying to figure out how to manipulate this divider core. I've ran a few tests where I modified the MAXIMIZE_SPEED parameter in an attempt to increase my slack. After a few iterations of running synthesis and PAR, it appears that changing this parameter does absolutely nothing. The fitter report and TimeQuest numbers all remained the same. Can anybody offer some information/help on how to get this core working efficiently and to pass timing?
