LPDDR5 single VDD2 rail mode - why is it not supported?

A knowledge base article was published on Jan 30,2026 that says Agilex-5 EMIF does not support single-rail VDD2 for LPDDR5. Can you provide more information about this restriction?

The choice between single-rail and dual-rail VDD2 configuration should be  dependent on whether the application is using DVFS - Dynamic Voltage and Frequency Scaling. DVFS is a low-power mode which can be selected when the data rate is 1600 Mb/s or less. The memory controller sends a mode register command to the memory to transition to DVFS mode. When that happens, the memory IC will switch the power source for the internal circuitry from the VDD2H (1.05V) pins to the VDD2L (0.9V) pins. So, when DVFS mode is active, the internal circuitry is operating at 0.9V, and the data rate is lower, so there is a power savings.

If the application has no use for the lower power mode, DVFS is not required. In that case, the VDD2L pins can be connected to 1.05V and the result is 'single-rail VDD2 mode'. The memory controller will know that DVFSC mode is not required, so it will never activate it.

My design has no use for DVFS mode and the power savings it provides is not worth it for my design. Therefore, I have implemented single-rail VDD2 mode in my Agilex-5 design, using A5EC043AB32AE2V. This means VDD2H and VDD2L are both powered at 1.05V.

This conflicts with the knowledge base article which says that my design must implement dual-rail VDD2 mode. Can you tell me the restriction in the memory controller which forces the use of dual-rail VDD2 mode, even though I don't want it? Is Altera saying that the memory controller has enabled DVFS mode internally and there is no way to disable that mode?

My design is in layout and will be released to manufacturing soon. If I have to add a 0.9V regulator for dual-VDD2 mode, I need to act now to change the design.  I would prefer to continue using single-rail mode if possible.

If I absolutely must use dual-rail mode, do you know if the LPDDR5 will be OK if VDD2L is 1.05V instead of 0.9V? I realize there will be no power savings in this case, but I don't care about that.