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MSe's avatar
MSe
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2 years ago

LP-HCSL Clock Buffer Output on a Dedicated Clock Input Pin - Arria 10 GX 160

Dear Intel Support Team, I am having some trouble designing my LP-HCSL Clock Signal to a Dedicated Clock Input, with regard to the available standards. My setup: Intel FPGA 23.2.0.94 Pro Edition...
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AqidAyman_Altera's avatar
AqidAyman_Altera
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2 years ago

Hi Marcel,


Any update on the suggestion from @FvM? Have you tried it?


  • MSe's avatar
    MSe
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    2 years ago

    Hi @AqidAyman_Intel ,

    thanks for keeping up with me on this topic.

    The Arria 10 docs seems to me a little bit inconsistent or rather incomplete regarding the

    DC-Bias and termination for the none ACVR Banks. So I assumed the worst and designed

    a DC-Bias in my schematic. With the first PCB batch I will see if it's working as intended.

    Best

    Marcel