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Occasional ContributorLow Latency 100G Ethernet Intel FPGA IP Hardware Design Example
Hi everyone,
I want to create a loop between 2x Low Latency 100G Ethernet Intel FPGA IP Hardware Design Example on a Stratix 10 MX. The main idea is to implement the entire example design described in alt_e100s10.v twice inside a top level module. The only doubt is given by the avalon jtag master bridge. Can i instantiate two of them, one for each instance? And if not, can i use the Ethernet Link Inspector for the two different instances with only 1 avalon jtag master bridge?
If i was not clear enough, please ask me questions.
Thank you.
12 Replies
AGaru1Thanks for your answer.
If i correctly understood i can use two Avalon Jtag master bridges, one for each Ethernet IP, as long as they have a different base address.
SengKok_L_IntelRegular Contributor
Hi,
Yes, you can use Avalon Jtag master bridge for more than 1 Ethernet IP, what you need to do is to ensure it has a difference base address.
Regards -SK
