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AGaru1's avatar
AGaru1
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6 years ago

Low Latency 100G Ethernet Intel FPGA IP Hardware Design Example

Hi everyone, I want to create a loop between 2x Low Latency 100G Ethernet Intel FPGA IP Hardware Design Example on a Stratix 10 MX. The main idea is to implement the entire example design described ...
AGaru1's avatar
AGaru1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Thanks for your answer.

If i correctly understood i can use two Avalon Jtag master bridges, one for each Ethernet IP, as long as they have a different base address.