Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorLoop index overflow problem
Hi there,
I've wrote a little VHDL program in Quartus II. I'd like to separate one big std_logic_vector into small fix-length std_logic_vectors and the compile told me that the index is out of range, very strange... source code: =================================================== load_p:process(i_clk,i_datain) variable p_count:integer range 0 to 8*8*i_width; --i_width is a constant variable p:std_logic_vector(i_width-1 downto 0);--buffer of one data begin p_count := 8*8*i_width-1; --counter for index for i in 0 to 63 loop p := datain(p_count downto p_count-i_width+1); --buffering (line 30) p_count := p_count-i_width; --get next line index end loop; end process; ======================================================= the compiler says: Error (10528): VHDL error at df_loader_p.vhd(30): value "-1" is outside the target constraint range (0 to 512) Help me out , thx!!!:(21 Replies
Altera_ForumA pretty long thread for a trivial overflow problem I think...
By the way, this was my original suggestion. Almost obvious in my opinion. "calculate the p_count value at the entry of each iteration"for i in 0 to 63 loop p_count := (8*8-i)*i_width-1; ... end loop;- Altera_Forum--- Quote Start --- yes, and just like in the C, you have the extra p_count := p_count+i_width which pushes p_count to 512 as the loop exits. you have exactly the same thing with j. It ends the loop on 512. --- Quote End --- ok, i understand, the iteration actually enter the overflow situation and then exit
- Altera_Forum
yes, and just like in the C, you have the extra p_count := p_count+i_width which pushes p_count to 512 as the loop exits.
you have exactly the same thing with j. It ends the loop on 512. - Altera_Forum--- Quote Start --- thats because j stops at 504, and you print j+7 I dont see a p_count + 7 offset anywhere in your VHDL. You'll find that j actually finishes the loop on 512. --- Quote End --- i wrote this, p := datain(p_count+i_width-1 downto p_count); --i_width=8, so this is my "p_count+7" p_count:=p_count+i_width;
- Altera_Forum
thats because j stops at 504, and you print j+7
I dont see a p_count + 7 offset anywhere in your VHDL. You'll find that j actually finishes the loop on 512. - Altera_Forum
int i,j;
j=0; for(i=0;i<=63;i++){ printf("%d,%d,%d\n",i, j,j+7); j+=8; } the last line of the output is 63,504,511 - Altera_Forum--- Quote Start --- How can it stop at 511 when you add 8 each time? --- Quote End --- because i only have 64 iterations, and started from 0, the last data bit range should be 504 to 511. i have ran this similar algorithm in C Code, the iteration stop at 511, no error appeared.
- Altera_Forum
How can it stop at 511 when you add 8 each time?
- Altera_Forum--- Quote Start --- You have changed the constraint range - in the origional code you posted : variable p_count:integer range 0 to 8*8*i_width; --i_width is a constant Which should give you 0 to 512. --- Quote End --- that is because the iteration should stop at 511
- Altera_Forum
No - the synthesisor ignores the sensitivity list. It will warn you if there are signals missing from the list, but it makes no difference to the logic created.
