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Altera_Forum
Honored Contributor
Honored ContributorLoop index overflow problem
Hi there, I've wrote a little VHDL program in Quartus II. I'd like to separate one big std_logic_vector into small fix-length std_logic_vectors and the compile told me that the index is out...
Altera_ForumHonored Contributor
Honored ContributorNo - the synthesisor ignores the sensitivity list. It will warn you if there are signals missing from the list, but it makes no difference to the logic created.
