Honored Contributor
Honored ContributorNo problem with the English. If you could though, in future posts, try to put down as much information about your situation as possible. If a ROM was implemented in Acex, there most likely isn't any problem porting it forward to SII/SIII. The only possibility I can think of is I believe Acek RAM had a purely asynchronous read/write mode, where the block rams are synchronous(SIII LUTrams have asynch reads, if you use those). And you can use .hex for these devices too.
If the design worked in Acex, retarget the compile for Stratix and see what happens. If it already exists, I see no reason to redo everything. But my adivce from before(using the Megawizard to create a ROM, or inferring it in HDL) is still relevant, and can be studied more in the Quartus II Handbook.
