Honored Contributor
Honored ContributorI think we're confusing each other with terminology. By LUT, I am refering to the Look Up Table before the register within the FPGA, i.e. a 4:1 LUT in Cyclone families, and an adaptive LUT in Stratix II/III. I would not recommend mapping directly to those low-level primitives unless you can't do it any other way.
I think what you are building is a ROM(which can alse be called a Look Up Table). In general, I would recommend using the Megawizard Plug-In Manager to build a ROM. You can use initialization files like .mifs, which are sometimes easier when repeating long ranges. The Quartus II handbook also shows how to infer ROMs out of logic, and how to add attributes that point to .mifs. As for doing pure VHDL, I'm not sure how to specify a range across the ROM. There's probably some slick way, but you could also just wrap it in for-loops and get the same result.
