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Altera_Forum's avatar
Altera_Forum
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15 years ago

Looking for Stratix 3 pin documentation

Hi, I fail to find information on the DDR Input and Output register capabilities of the Stratix 3, L110 FPGA, device EP3SL110F1152C3. I need to know whether a given pin has DDR capabilites...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Ok, maybe we can solve the issue without documentation: I have a fit error with this message:

Error: Can't assign node "<design_top>|alt_iddr:\gen_dout:1:alt_iddr_3|altddio_in:altddio_in_component|ddio_in_sqi:auto_generated|ddio_ina[0]" to location IOPAD_X91_Y42_N0 -- node is type Double data rate I/O input circuitry

So I assume the Stratix 3 FPGA does not have DDR capabilities on this pin. Could there be another reason that Quartus can't fit this? If so, how could I find out about that.

Best regards

flint