Looking for state machine in verilog

Does your logic state machine is working?

I have my code here and hope you could find error in my code...

localparam State1 = 0;

localparam State2 = 1;

reg [31:0] rCntr;

reg [15:0] rTmCntr1, rTmCntr2;

reg wPwm, StateSignal, SwitchSignal;

initial begin

rTmCntr1 = 0;

rTmCntr2 = 0;

rCntr = 2000000;

wPwm = 0;

StateSignal = State1;

SwitchSignal = 0;

end

always @(posedge c0) begin

if (SwitchSignal == 1)

StateSignal = State2;

end

always @(posedge c0) begin

if (StateSignal == State1) begin

// code for State1

if (Enable == 1'b1) begin

rTmCntr1 <= rTmCntr1 + 1'b1;

if (rTmCntr1 < 2500)

wPwm <= 1;

else if (rTmCntr1 > 2500)

wPwm <= 0;

if (rTmCntr1 == 5000)

rTmCntr1 <= 1'b0;

end

if (rCntr > 0)

rCntr <= rCntr - 1'b1;

else if (rCntr == 10)

SwitchSignal = 1;

end

else begin

// code for State2

if (Enable == 1'b1) begin

rTmCntr2 <= rTmCntr2 + 1'b1;

if (rTmCntr2 < 1250)

wPwm <= 1;

else if (rTmCntr2 > 5000)

wPwm <= 0;

if (rTmCntr2 == 5000)

rTmCntr2 <= 1'b0;

end

end

end

Thanks,

Sean