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. I'm learning about testbenches and from what I have read you can set up the test bench to run thousands of read/write transactions and have the test bench verify each transactions. This appeals to me because I won't have to scroll through waveforms trying to decipher if these are working.
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That's precisely what we advice to our customers - whatever you "eyeball" in waveform, capture them using assertions (SVA or PSL). This would help in automating checks during simulations.
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I've been reading about the SystemVerilog Verfication model and was wondering if I only want to automate my testing will SystemVerilog assertions be sufficient?
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Depends on what you mean by "testing" - the "checker" portion of it to a large extent can be captured with Assertions. For generating intellignet stimulus and modeling reusable testbenches you will require more capable features from SystemVerilog such as classes, constraints, functional coverage etc.
I recommend you read some of the advanced verification challenges in forums like
verificationguild.com,
cvcblr.com/blog etc. But since you are just starting to explore, it will be a good idea to get going with SVA/PSL and then take up full SV once you see value.
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This would reduce the cost of the simulator. To implement everything described in SV for Verification drives up the cost of a simulator.
Thanks,
joe
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In general YES, but given the availability of more tools with SV support, it is becoming more competitive for EDA vendors thereby bringing down the cost. If you have good negotiator you may be able to get few SVA-enabled tools and few full-SV enabled tools.
Good Luck
Srini
cvcblr.com/blog
Honored Contributor
