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bigcheesefuzz's avatar
bigcheesefuzz
Icon for New Contributor rankNew Contributor
7 years ago

Long counter (30s) in VHDL, balancing a clock divide and counter size

I need to add a timer to an application running on a Cyclone V with a long (30s) period.

I can easily write an integer counter that counts the clock (30MHz) x 30s = 90,000,000 which uses ~150 LUTs.

However I'm looking to reduce the amount of LUTs, I can divide the 30MHz clock down (say 100 or 1000) and the my counter only need to count the equivalent amount.

Are there any rules / guides to the ratio of clock divide-to- counter size to best implement a design ? Particularly for the smallest amount of LUTs ?

Plus running the counter slower would surely better from a timing perspective ?

1 Reply

  • ak6dn's avatar
    ak6dn
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    If you need just a fixed duration counter (ie, don't need to load arbitrary count values) I would examine use of an LFSR approach to use a minimal number of cells. The number of cells will basically track the length of the counter. A 30 bit counter could have a period of 2^30-1 clocks (this is what is know as a maximal length LFSR). Here is a good quick reference: https://en.wikipedia.org/wiki/Linear-feedback_shift_register