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Honored ContributorLogic lock
How to make many logic locks that are exactly the same as one logic lock?
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Altera_ForumHonored Contributor
Honored ContributorI exported logic lock:
load_package flow load_package logiclock load_package backannotate project_new lockmult -overwrite set_global_assignment -name BDF_FILE pipemult.bdf set_global_assignment -name FAMILY CycloneII set_global_assignment -name DEVICE EP2C35F672C6 set_global_assignment -name TOP_LEVEL_ENTITY pipemult# These two assignments cause the Quartus II software# to generate a VQM file for the logic in the LogicLock# region. The VQM file is imported into the top-level# design. set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_FILE pipemult.vqm set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT ON create_base_clock -fmax 200MHz -target clk clk_200# assign_virtual_pins { clk }# Prepare LogicLock data structures before# LogicLock-related commands. initialize_logiclock# Create a region named lockmult and assign pipemult# to it.# The region is auto-sized and floating. set_logiclock -region lockmult -auto_size true -floating true set_logiclock_contents -region lockmult -to pipemult execute_flow -compile# Back annotate the LogicLock Region and export a QSF logiclock_back_annotate -region lockmult -lock logiclock_export -file_name pipemult.qsf -routing uninitialize_logiclock project_close and then import: load_package flow load_package logiclock project_new topmult -overwrite set_global_assignment -name BDF_FILE topmult.bdf set_global_assignment -name VQM_FILE pipemult.vqm set_global_assignment -name FAMILY CycloneII set_global_assignment -name DEVICE EP2C35F672C6 create_base_clock -fmax 200MHz -target clk clk_200# The LogicLock region will be used four times# in the top-level design. These assignments# specify that the back-annotated assignments in# the QSF will be applied to the four entities# in the top-level design. set_instance_assignment -name LL_IMPORT_FILE pipemult.qsf -to pipemult:inst1_1 set_instance_assignment -name LL_IMPORT_FILE pipemult.qsf -to pipemult:inst1_2 set_instance_assignment -name LL_IMPORT_FILE pipemult.qsf -to pipemult:inst1_3 set_instance_assignment -name LL_IMPORT_FILE pipemult.qsf -to pipemult:inst1_4 set_instance_assignment -name LL_IMPORT_FILE pipemult.qsf -to pipemult:inst1_5 set_instance_assignment -name LL_IMPORT_FILE pipemult.qsf -to pipemult:inst1_6 set_instance_assignment -name LL_IMPORT_FILE pipemult.qsf -to pipemult:inst1_7 execute_flow -analysis_and_elaboration initialize_logiclock logiclock_import -do_routing uninitialize_logiclock execute_flow -compile project_close And then I instantiate the pipemults using VHDL. Why the logic, routing and position of logic in the logic lock region changed?
