Logic error? Code error?

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Hello people,

So this is my problem. I am designing a module which is basically reading from a device. Now, depending on the inputs to this module, it access different parts of the device.

if rtc_state = s0 then
	if hmi_en = '1' then
		if hmi_rdwr = '1' then
			rtc_state <= sHMI_rd;
			buff_hmi_addr <= hmi_addr;  
		else
			rtc_state <= sHMI_wr;
	                buff_hmi_addr <= hmi_addr;
			buff_hmi_data <= hmi_data;
		end if;
	elsif rd_wr = '0' then
		rtc_state <= sWr;
		buff_addr <= addr; 
		buff_data <= data;
		flag_wr <= '1';
	elsif rd_wr = '1' and SQW = '1' and U_EN = '1' then
		rtc_state <= s1;
	else
	        rtc_state <= s0;
	end if;
end if;

Well, i've narrowed down the problem to this piece of code. Actually, i get a warning that signals dependent on the signal hmi_en are stuck to ground. Also, if i change the statement

if hmi_en = '1' then

to

if hmi_en = '0' then

then all the other states become redundant because the damn thing seems to be stuck to GND.

Note: hmi_en is an input which is coming from port.

Any/All help is appreciated.

Thanks & Regards,

Yash

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Hi ,

maybe it is a stupid question, but do check that the signal hmi_en is really connected to the port ? No type mismatch ? Be aware that Verilog is case sensitive.

Hi,

The code itself seems ok but...

First: the signal hmi_en seems stuck to '0' and is never '1'.

Second:You are not following a standard state machine template, assuming you are doing a state machine.

Kaz