Honored Contributor
Honored ContributorThe least painful may be ethernet. If you have a licence for the core, then you should be able to get PC side drivers for it, it would plug straight into an FPGA side SoC system if needed, or you can just do some packet processing on the FPGA to get the data out. Its not all that hard, its just about learning where all the headers are for Rx, and generating the headers for Tx. What is a lot of work is the testing and verification, as an out of place header will just mean you start losing data (or break the system).
What level of processing did you have to do with the PCIe core? were you processing the TLP packets, or did have a MM interface at the FPGA end?
