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Hey ppl,
I want to learn FPGA design, I even bought development board DE2.
What I need now is a good source of information. I understood that the most famous HDL language is Verilog. I know it a little bit.
What I need is to learn how is to describe the system functionality in the right way, what is the right way to write test benches, and so on.
Do you know where can I get this information in the best way described?
Thanks ahead
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BadOmen already gave excellent advice. Any design has data flow and control logic and the control logic is the key to the functionality. The System has inputs, data manipulation, and outputs. So if you put together what is necessary to explain your new system to someone else, you will have a good start. HDL is a description language in text format that is used to define the hardware to the EDA programs that convert to physical circuitry. In the process Register Transfer Level data are generated and simulation can then produce waveforms for the test bench.
The test bench applies inputs and generates simulated outputs. To verify a design exhaustively the test bench would have to have every combination of inputs for the system ... it may practical to partition the system so the partitions can be verified independently with overall verification at a higher level.
Recently there was a thread started by BuGless about HDL vs Schematic design entry and it seems that starting with a block/flow diagram for the big picture then using HDL for the detailed design may work pretty well. It was a long discussion, but food for thought.
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