Learn FPGA design

Back in the day I learned VHDL using the tutorials built into the Aldec tools. They go though various levels in an automated tutorial type of flow. That was a long time ago but I hear they still have it and if it was good back then it must be even better by now.

One really important thing in my opinion is to find HDL examples that use a clean style (just like in software). I learned verilog the hard way and picked up all kinds of bad styles along the way when starting out. I use a really ridged style now where I separate everything combinational from the register assignments which avoids all the gotchas that verilog offers. This method is very handy (I think) because any time I want to change the control behavior it's all located in one spot and I don't need to touch anything in the register portion of the code. It also prevents doing foolish things like creating latches by accident since that's a big no-no when it comes to FPGA design usually. Here is an example of what I'm talking about: http://www.altera.com/support/examples/nios2/exm-modular-scatter-gather-dma.html Any time I update that design I can literally look at a single screen of combinational assignments to fix bugs or add enhancements without even looking at the mess of registers and submodule instantiations that reside above the combinational code. For those of you in school you might hear the term "RTL" as in "register transfer level" taught ..... that's what I just described and when it comes to large scale design I consider it the *only* style worth using.