latch warning using unconventional programming style in VHDL

Hi all, I use an unconventional programming style. My FPGA designs work almost without problems. However, in the synthesis I get the warning message: "inferring latch(es) for signal or variable" r ", which holds its previous value in one or more paths through the process".

It makes sense for me, as it is registers within the record, which may not change their value. Does this possibly affect the created FPGA circuit?

The code below is just a basic example, regardless of syntax errors.

entity modul_abc is
port(
    clk: in std_logic;
    rst_n: in std_logic;
    input_in: std_logic_vector(3 downto 0);
    output_out: std_logic_vector(3 downto 0)
 );
end entity; 
 
architecture arch of modul_abc is
 
type T_REG is record
  abc : natural;
  efg: std_logic;
  xyz : std_logic_vector(3 downto 0); 
end record;
 
constant C_REG_DEFAULT : T_REG := (
  abc => 0,
  efg => '0',
  xyz => (others => '0')
);
 
signal r : T_REG := C_REG_DEFAULT;
 
begin
 
 output_out <= r.xzy;
 
process(rst_n, clk)
    variable v : T_REG := C_REG_DEFAULT; 
begin
    if rst_n = '0' then
        r  <= C_REG_DEFAULT;
    elsif rising_edge(clk) then 
        v := r;
        v.abc := r.abc +1;
        v.xyz := input_in;
        r <= v;
    end if;
end process;
end architecture;