Forum Discussion
CStoe2
New Contributor
New Contributorlatch warning using unconventional programming style in VHDL
Hi all, I use an unconventional programming style. My FPGA designs work almost without problems. However, in the synthesis I get the warning message: "inferring latch(es) for signal or variable" r ",...
sstrell
Super Contributor
Super ContributorIt is bad practice to infer any latches, especially because they can cause a mismatch between simulation and synthesis. My question is why do you even need the variable v? Just update r.abc and r.xyz directly each clock cycle. But to avoid the inferred latch, you could probably just add: r.efg <= r.efg;
#iwork4intel
CStoe2I see, I made a mistake. I used a two process method since my first FPGA days as described here:
https://www.gaisler.com/doc/vhdl2proc.pdf
I thought these programming style could combine the advantage of this method, using r for actual state and v for further register state, in a process. But this seems not to work in the same way.
