Latch Inferrence

Hey guys,

Lets say you have a simple state machine output assignment block like the one below:

 
always @(pstate)
begin
       case(pstate)
 
                    s0:
                    begin
                    out1<=0;
                    out2<=1;
                    end
 
                    s1:
                    begin
                    out1<=1;
                    out2<=0;
                    end
 
                    default:
                    begin
                    out1<=0;
                    out2<=0;
                    end
             endcase
end
 

When you compile the above code, you get infered latches for the outputs, which are bad.

How can I get around this? I don't want to use simple assign statements for the outputs, because the idea is to keep the value of a signal until a different state arrives.

For example, if I am in state 0, I want out2 to remain high until s1 is reached. Of course, this requires memory. But I don't want to infer latches. And if I use a posedge clock in the sensitivity list, I get unexpected results.

Any ideas would be greatly appreciated.