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Those are simply padding bits being transmitted by the host until it receives the CONFIG_DONE signal, or until detects an error condition.
If you take a look to data line, you see a sequence of 0xFF bytes.
This is usually done because some devices nuse extra clocks for startup timing
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I don't use a host device. I use a MCU for reading the bitstream from a spi flash memory and programming the fpga. I see that last bits exist in the .rbf file and also in the .hexout file.
Also, on the PS configuration datasheet, it is written that 2 more DCLK pulses are needed after Config Done pin is High to enter Initialization Mode.
I will add these 2 more clk pulses but now it seems that is is not needed..
Do you mean that last FF bytes are dummy bytes for sending blank clock pulses?
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