jtag user0/user1 registers in VHDL logic

Question

How do I define the jtag user0/user1 registers in my vhdl code on CycloneIV?

What are the signal names are for at least tdi/tdo and the 'shiftdr' state, for use from VHDL?

In other words, what is Altera's version of Xilinx's 'bscan' component?

I have searched, but only found references to 'virtual jtag megawizards', which (as far as I understand)

build a huge edifice on user0/user1, when I just want to use user0/user1 'raw'.

altera_forum · Answer

The Altera equivalent of the BSCAN component is the SLD_Virtual_JTAG component. You don't need to explicitly use USER0/USER1 instructions like with BSCAN. Altera has created an infrustructure where multiple JTAG components can share a common USER0/USER1 instruction register. Take a look at the JTAG analysis on this page:

https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html

The SLD JTAG is analyzed in

https://www.ovro.caltech.edu/~dwh/correlator/pdf/vjtag.pdf

But it turns out that the JTAG-to-Avalon-MM bridge is pretty generically useful, so if you use that, along with Qsysa, you can pretty much build anything you like.

Cheers.

Dave

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jtag user0/user1 registers in VHDL logic

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