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Altera_Forum
Honored Contributor
Honored ContributorJtag uart causes "Verify failed" error
When I try to run or debug my application on my DE3 board, I get the following error: Using cable "USB-Blaster [USB-0]", device 1, instance 0x01 Processor is already paused Reading System I...
Altera_ForumHonored Contributor
Honored ContributorIs your design properly constrained? Have a look at the Timequest report, especially the clocks and unconstrained paths. If the clocks aren't defined properly, then you can have a compile without critical warnings, even if the timing is bad.
Are you sure the second CPU isn't writing something to the first CPU's instruction memory between the download and verify phases?
