Hi, The main issue i want to ask is whether the jtag to avalon master bridge IP core can be used to communicate data between PC and the FPGA, even if the board does not have JTAG connector. My board is terasic de4, and it has only a USB blaster, which can be configured in JTAG mode. I need to write some registers in the FPGA through System Console using master_write_32 command. I made a design with jtag to avalon master bridge as master to write to some Memory Mapped slaves. Can this be done through the USB blaster in JTAG mode or does the board need additional JTAG connecter for this functionality. Thanks in advance

Hi, Thanks a lot for the reply. I tried communicating through system console, but was getting some errors. set jtag_master [lindex [get_service_paths master] 0] open_service master $jtag_master The above two commands worked properly. But when i tried the command master_write_32 $jtag_master 0x400 0x00000000, i am seeing the following error. error: java.lang.RuntimeException: This transaction did not complete in 60 seconds. System Console is giving up. while executing "master_write_32 $jtag_master 0x400 0x00000000" What could possibly be a reason for this error. is_service_open command returns 1. Thanks in advance

Have you got any other jtag services that can be seen as master 0? (It happened to me that the 0 position in the list was occupied by Nios2; it only happened once and I do not know why). Are you sure the slave you are addressing is compliant to avalon specifications? If it is a custom one, try putting a SignalTapII instance and watch if the handshake on the avalon slave interface proceed as you expect.

The first thing I would check if you're getting this kind of error is that your clocks are running and resets are releasing properly. If the first access fails that is normally the cause. You can use the jtag_debug commands to do this, or if that doesn't help then I'd go for SignalTap next.

Hi, Thanks a lot guys. The issue was with my clock. I found the clock which i had assigned not toggling in the Signal Tap. I changed the assignment and it is working fine now. Regards Hari

JTAG to Avalon master bridge usage | Altera Community

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Altera_Forum
Honored Contributor
14 years ago
I think you said you were building the fabric using QSYS? I'm pretty sure that QSYS does not support native addressing, it treats native slaves as if they were 32 bit dynamic slaves. This looks the same to 32 bit masters (Nios II, JTAG Avalon Master etc). If you had managed to enable native addressing then this would not cause the issue with reads and writes behaving differently.

If the address mapping is different for writes and reads then this could be a bug. Can you signaltap the signals on the JTAG Avalon master as well as on your slave please - the master address should match the address passed in from SystemConsole for both writes and reads.

The byteenable behaviour you'll get depends on how you wrote your hw.tcl file. If you specified that your port was for role (not signal name) byteenable_n then 2'b00 is both bits asserted. If your add_port command specifies an active high byte enable then I would expect 2'b11. Again, measuring on the master will help debug here.
Altera_Forum
Honored Contributor
14 years ago
Thank you so much. My signal tap file was triggered by wrong signals. I do have same address mappinf for both reads and writes.

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JTAG to Avalon master bridge usage

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