JTAG to Avalon master bridge usage

I think you said you were building the fabric using QSYS? I'm pretty sure that QSYS does not support native addressing, it treats native slaves as if they were 32 bit dynamic slaves. This looks the same to 32 bit masters (Nios II, JTAG Avalon Master etc). If you had managed to enable native addressing then this would not cause the issue with reads and writes behaving differently.

If the address mapping is different for writes and reads then this could be a bug. Can you signaltap the signals on the JTAG Avalon master as well as on your slave please - the master address should match the address passed in from SystemConsole for both writes and reads.

The byteenable behaviour you'll get depends on how you wrote your hw.tcl file. If you specified that your port was for role (not signal name) byteenable_n then 2'b00 is both bits asserted. If your add_port command specifies an active high byte enable then I would expect 2'b11. Again, measuring on the master will help debug here.