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Altera_Forum
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8 years ago

JTAG timing constraints

Hi, Over the years my company has made many Altera FPGA designs, and for a long time the way-of-work for JTAG constraints remained undefined and of little consequence. Then for a couple Arria ...
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Altera_Forum
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8 years ago

Hi

Are you using Max 10 device?

Can you attach the screen short of the schematic jtag configuration sheet?

what is the voltage given on 4th pin for Jtag header?

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)