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Altera_Forum
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8 years ago

JTAG timing constraints

Hi, Over the years my company has made many Altera FPGA designs, and for a long time the way-of-work for JTAG constraints remained undefined and of little consequence. Then for a couple Arria ...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Hello All,

I wonder if there's been any further progress or a 'definite conclusion' on this matter?

I recently did a prototyping-board and ran into JTAG configuration issues, mainly the value of VCC, to which the pull up resistors had to be pulled up (as per Max 10 'Pin Guidelines' document). These were the resistors on the 4 JTAG signals and the 3 configuration resistor (nConfig, nStatus and ConfigDone pins).

After I fixed these issue on the proto board, JTAG configuration always worked on my one proto board and still does.

I made same fixes on new version of boards (new pcb layout), though 1 or 2 of the JTAG signal likely increased slightly in trace-length, but really no other change. Unfortunately on the new version board (tried only one board yet), JTAG configuration is failing with nStatus always staying low, indicating that JTAG FSM is stuck in the 'reset' state. However I am able to read the 'device ID' when trying to configure, so I assume JTAG signals on the FPGA are working.

Here are some other points:

- TCK frequency is 6MHZ (As per other info out there, I could change that to 16 or 24MHz as I am using Blaster-II, using 'jtagconfig' utility in the command line, but I have been unable to do that. Nevertheless 6MHz is the slowest rate, but I wanted to try faster rates on my Proto board so see how fast I can go, where it is working. The new boards are 'nearly identical' in terms of JTAG trace-lengths and trace-widths).

- I am using USB-Blaster II (Rev B. The ribbon cable length on it is about 8 inches. I read somewhere reducing it a lot may help but have not tried it yet.

- I not using 'diodes and caps' on the JTAG lines, as recommended by Altera / Intel to suppress 'voltage overshoot', on either of the boards. However Altera documents states that they are Only needed if JTAG connector supply (jtag connector pin# 4) is Over 2.5V and I am only using 2.5V supply on both the boards.

- I am using a UBGA chip, so cannot probe FPGA pins directly, but since I am able to get Device ID, I am assuming JTAG pins are alive and working

Thanks a lot!