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Altera_Forum
Honored Contributor
Honored ContributorJTAG timing constraints
Hi, Over the years my company has made many Altera FPGA designs, and for a long time the way-of-work for JTAG constraints remained undefined and of little consequence. Then for a couple Arria ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The weird thing is that the JTAG signals are hard, fixed paths, so it doesn't make sense that timing constraints should have any affect on them all. --- Quote End --- I'm inclined to agree that JTAG constraints should not affect the design at all. At best it would serve as a check that your hardware delays and clock frequency are viable i.c.w. the fixed FPGA paths. My experience tells me though that the JTAG constraints *do* affect JTAG stability.
