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Altera_Forum
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8 years ago

JTAG timing constraints

Hi, Over the years my company has made many Altera FPGA designs, and for a long time the way-of-work for JTAG constraints remained undefined and of little consequence. Then for a couple Arria ...
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Altera_Forum
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8 years ago

Hello Daniel,

Do you use original Altera USB Blaster?

The best reliable source is TimeQuest Analyzer Cookbook that is written by Altera.

In DE1-Soc I have found an example with these constraints: 

# for enhancing USB BlasterII to be reliable, 25MHz
create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}
set_input_delay -clock altera_reserved_tck -clock_fall 3 
set_input_delay -clock altera_reserved_tck -clock_fall 3 
set_output_delay -clock altera_reserved_tck 3

So you are not alone with JTAG problems on unconstrained designs. Actual values of constraints depends on your hardware (jtag connector to FPGA routes).

Best regards,

Leonardo