jtag question

Hello, I need to know one data from USB-Blaster.

The USB-Blaster Specification shows the diferents pins that have to connect to the nios II development board stratix II version (jtag connector)

The pin 4 are VCC (TRGT). I need the value that has this pin. The table of specification says: "stratix II --> As Specified by Vccsel."

I found information about Vccsel on the stratix II handbook, but i don't understand it.

"The VCCSEL pin selects the type of input buffer used on configuration input pins and it selects the POR trip point voltage level for VCCIO bank 3 powered by VCCIO3 pins.

For more information, refer to Table 7–24 on page 7–105.

The configuration input pins and the PLL_ENA pin (Table 7–5) have a dual buffer design. These pins have a 3.3-V/2.5-V input buffer and a 1.8-V/1.5-V input buffer. The VCCSEL input pin selects which input buffer is used during configuration. The 3.3-V/2.5-V input buffer is

powered by VCCPD, while the 1.8-V/1.5-V input buffer is powered by VCCIO. After configuration, the dual-purpose configuration pins are powered by the VCCIO pins of the bank"

as I can know the value of vccsel?

In the table 7-24 says that the diferents pins are powered by the 3.3-V Vccpd supply.

Which value are the correct for the Vcc (TRGT) on the nios II development board with a stratix II fpga???

thanks for your replay and sorry because i don't place correctly the post but i newbie.