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Altera_Forum's avatar
Altera_Forum
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17 years ago

JTAG header conections

Hi, I am new to FPGA design, so this question might look easy. but it will be of great help if anyone can clarify this doubt. I want to have JTAG interface for the Cyclone III on the board. I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Well here is what I could find:

From the pin connection guidelines for Cyclone III regarding the TMS and TDO signals:

--- Quote Start ---

When interfacing with 2.5V/3.0V/3.3V configuration voltage standards, connect

this pin through a 1-kOhm resistor to VCCA. Otherwise, connect this pin through

a 1-kOhm resistor to VCCIO. See Note (4).

--- Quote End ---

Also reference Figure 10-24 on page 10-57 of the Cyclone III device handbook.

It sounds to me like they want you to use the 2.5V VCCA if the VCCIO for the bank is 2.5V or higher. If the VCCIO for the bank is lower than 2.5V, use VCCIO instead. The only purpose for this voltage is to power the level translators on the USB Blaster which drive the TDI, TDO, TCK, and TMS pins. Ideally of course the voltage you drive on TDO should match this standard. However, the USB-Blaster is pretty forgiving when it comes to TDO.

Jake