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Altera_Forum
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17 years ago

JTAG configuration protocol specification

Hello,

We're in the process of debugging a JTAG configuration problem (Quartus doesn't recognize the chain that consists of a single CycII device). We try to look at the TDI, TMS, TCK, TDO lines and see if they behave per spec.

However, there seems to be no complete specification of the JTAG configuration protocol used by the USB blaster to configure the device. The device datasheed and the Configuration Handbook give only basic information without getting into details.

Is there a different place I should look at ? Or am I missing the specification in the documents I listed ?

Thanks in advance

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I'm not sure if there is a formal specification for JTAG configuration, but Altera provides source code for the JRunner Software. It is available for download in the Download Software section.

    OTOH, the USB Blaster specifications are completely undisclosed.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Checking the chain continuity is a very basic JTAG operation, not specific to Altera devices in any way. The JTAG access algorithm is described in various Altera documents (and a nearly inifinite amount of internet resources).

    Not recognizing the chain means that one of the four signals is either unconnected, wrongly connected or shorted. Almost easy to grasp to my opinion. Another possible issue is a missing or out-of-specification supply, e. g. missing 2.5 V VCCA at a Cyclone III device.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    If you have done any soldering rework, it is possible that some residual soldering flux is creating electrical problems to the JTAG signals, it is a typical problem. If it is the case, try to accurately wash the board with a solvent.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    Checking the chain continuity is a very basic JTAG operation, not specific to Altera devices in any way. The JTAG access algorithm is described in various Altera documents (and a nearly inifinite amount of internet resources).

    --- Quote End ---

    I'm interested in finding out what Quartus does when I ask it to "Auto Detect" in the programmer and it comes back with the device IDs on the chain. Which set of JTAG commands it sends.

    Could you please point to those documents from altera and at least a couple of the most useful internet resources ? I've already went through everything in Altera's configuration handbook.

    --- Quote Start ---

    Not recognizing the chain means that one of the four signals is either unconnected, wrongly connected or shorted. Almost easy to grasp to my opinion. Another possible issue is a missing or out-of-specification supply, e. g. missing 2.5 V VCCA at a Cyclone III device.

    --- Quote End ---

    Thanks for the tips, we're working on finding out the problem. It is exaggerated by the fact that 3 boards that came from the plant show the same problem.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    3 boards may seem a hardware problem at a first glance. But once I had a problem with a defective batch of CPLDs which interrupted the JTAG chain. I have noticed this problem by replacing the CPLD with another one removed from a correctly working board.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Please have a look e.g. at Cyclone III manual chapter 14 BSDL. It's describing very detailed, how the IDCODE instruction is performed at the JTAG interface.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    3 boards may seem a hardware problem at a first glance. But once I had a problem with a defective batch of CPLDs which interrupted the JTAG chain. I have noticed this problem by replacing the CPLD with another one removed from a correctly working board.

    --- Quote End ---

    Yes, replacing the FPGA with one from a working board came up. BGA packages make it more challenging, however.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    From my personal experience I know that the first steps are:

    - 6 TCK cycles with TMS set to 1 to reset the TAP controller

    - TMS sequence 0100 to move to shidt DR

    - more than 100 TCK cycles to read the reset value of DR

    the JTAG ID code of the device should come out of TDO on the

    first 32 clock cycles

    is that enough for you?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    I'm interested in finding out what Quartus does when I ask it to "Auto Detect" in the programmer and it comes back with the device IDs on the chain. Which set of JTAG commands it sends.

    --- Quote End ---

    Again, check the Jrunner source code. That's not guaranteed to be exactly the same procedure used by Quartus, but it should be pretty close.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    What about your board's supplier testing method? Is he using JTAG inspection? I think that he should have noticed a JTAG chain interruption before delivering the boards to you.