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Honored Contributor
Honored ContributorJTAG chain debugger tools scripts & JTAG clock management
Hi everyone, For a design tests, I'm planning to implement this design to a Cyclone II FPGA (integrated to a DE1 board). I then would like to apply stimuli on DUT inputs via the JTAG chain an...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- How to synchronize my DUT internal registers and I/Os JTAG cells on the same clock? Or how can I be sure to correctly sample output pins with the JTAG chain? --- Quote End --- Just as you would with any other design that uses two clocks, you use clock-domain crossing logic. Eg., if its just one piece of info that needs to be transferred, you use a handshake with synchronizers, or if its lots of info, you use a FIFO. --- Quote Start --- Can I specify DUT clock state via JTAG and connect that signal to a normal pin (meaning non-clock dedicated pin) and then use it as clock for my DUT? --- Quote End --- If you have a clock for your DUT, then there is nothing special required, you simply use it. If that clock domain needs to transfer info to JTAG, then you need to use clock-domain crossing logic. This is all taken care of in the JTAG-to-Avalon-MM bridge, which is why I suggested using it. --- Quote Start --- I also though of connecting the DUT clock pin to the JTAG clock, but it would be quite complicated as my DE1 connections are buried in the card plastics. --- Quote End --- The JTAG clock comes from the USB-Blaster, there is no option or reason to change it. Cheers, Dave
