JTAG chain debugger tools scripts & JTAG clock management

I investigated deeper this DUT clock control problem and I found 2 solutions proposals (http://openocd.sourceforge.net/doc/html/faq.html):

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• solution# 1 - a special circuit
  In order to make use of this, your CPU, board, and JTAG adapter must all support the RTCK feature. Not all of them support this; keep reading!

• solution# 2 - always works - but may be slower
  Often this is a perfectly acceptable solution.
  In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of the target clock speed. But what that “magic division” is varies depending on the chips on your board. arm rule of thumb Most ARM based systems require an 6:1 division; ARM11 cores use an 8:1 division. xilinx rule of thumb is 1/12 the clock speed.

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I'm searching for a simple solution to my problem, I then prefer the second one.

In my case, the JTAG clock TCLK seems to run at 6Mhz (because using a USB-Blaster cable, see source here (http://www.alteraforum.com/forum/showthread.php?t=21914)) and the DE1 board has 27 and 50Mhz oscillators. If my design uses a 27Mhz clock and a 6Mhz JTAG clock, I will not correctly sample any fast signals (one clock period wide, for instance).

Quartus II tools are able to perfectly use JTAG circuit on DE1 board, I should have the possibility to do the same.

• does someone know how quartus tools manage jtag to correctly sample all output signals, or anything else about clock synchronization on an altera development board such as the de1?

• can i specify dut clock state via jtag and connect that signal to a normal pin (meaning non-clock dedicated pin) and then use it as clock for my dut?

About the second question I'll try to use a gated clock/synchronous clock enable circuitry between the board clock and the JTAG provided clock signal, I'll keep you updated!

Regards!

J-B