JTAG chain debugger tools scripts & JTAG clock management

Hi everyone,

I carefully read Dave's JTAG-to-Avalon tutorial and it was interesting, particularly the section over Qsys which I never used before.

This debug system is good but cannot be integrated to my design, question of requirements.

Instead of it, as I explained previously, I'm using low level JTAG interface with only the DUT on the FPGA to test it.

Thanks to Dave's Virtual JTAG interface tutorial, I use the device_dr_shift and device_ir_shift tcl procedure to read from and write to DUT I/Os.

i have however a problem with the device under test clock control / management via jtag.

Following Altera's cyclone II documentation, it seems that the dedicated clock input pins cannnot be drived by JTAG, but can be captured.

Which is OK with what Dave previously said:

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I'm also always searching for explanation about how the JTAG manages the DUT clock, when JTAG is active. Does it disable the clock, how is it done?

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The JTAG does nothing to the clocks, its completely independent of your top-level design's clock pins. If you want the signals from JTAG to be synchronous to your DUT clock, then you have to add the synchronization logic.

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Then, when I will set DUT inputs, I will not sample correctly the corresponding output, because registers will be clocked on my device clock, which is faster than JTAG clock.

My question is then :

• how to synchronize my dut internal registers and i/os jtag cells on the same clock? or how can i be sure to correctly sample output pins with the jtag chain?

• can i specify dut clock state via jtag and connect that signal to a normal pin (meaning non-clock dedicated pin) and then use it as clock for my dut?

I also though of connecting the DUT clock pin to the JTAG clock, but it would be quite complicated as my DE1 connections are buried in the card plastics.

In advance, thanks for your help!

J-B