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Honored Contributor
Honored ContributorJTAG chain debugger tools scripts & JTAG clock management
Hi everyone, For a design tests, I'm planning to implement this design to a Cyclone II FPGA (integrated to a DE1 board). I then would like to apply stimuli on DUT inputs via the JTAG chain an...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I have a DE1 --- Quote End --- Here's a basic top-level design and constraints file in the format I've used for the tutorial: http://www.alteraforum.com/forum/showthread.php?t=35687 Cheers, Dave
