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Altera_Forum
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14 years ago

JTAG chain debugger tools scripts & JTAG clock management

Hi everyone, For a design tests, I'm planning to implement this design to a Cyclone II FPGA (integrated to a DE1 board). I then would like to apply stimuli on DUT inputs via the JTAG chain an...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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I think using pure JTAG chain with DUT I/O better fits my requirements.

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Ok, so how are you going to set and clear individual bits?

Hmm, how about a block of registers? Ok, so first you'll need a shift sequence to load the address register, then a shift sequence to issue a read or write command, and then perhaps another shift sequence to read the result. Ah, but what about slow devices, how to you know when read data is ready?

By the time you've answered all those questions, you've re-written your own implementation of the JTAG-to-Avalon-MM bridge.

Read the Avalon analysis document. No matter how you implement your design, you have to implement much of the same functionality as already exists in the JTAG-to-Avalon-ST bridge, and then the JTAG-to-Avalon-MM bridge. I don't like some aspects of the design, but it works, so I just use it.

I'm not trying to sell this to you :) I'm just trying to point out that you have better things to do than to try and create some low-level JTAG components, when the components you need already exist.

Cheers,

Dave