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Honored Contributor
Honored ContributorJTAG chain debugger tools scripts & JTAG clock management
Hi everyone, For a design tests, I'm planning to implement this design to a Cyclone II FPGA (integrated to a DE1 board). I then would like to apply stimuli on DUT inputs via the JTAG chain an...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I didn't know it was possible to integrate Avalon systems to ASIC designs. Or maybe design effort should be carried out to replace it by another bus protocol? --- Quote End --- You're still missing the point. Think of the JTAG-to-DUT bridge as a black box. Its sole purpose in life is to give you some way of using a JTAG transaction to set bits and read the bits connected to your DUT. For the FPGA design, the JTAG-to-DUT bridge can easily be implemented using the JTAG-to-Avaon-MM bridge and PIO components. If you were using a Xilinx FPGA, you'd use a bscan component, if you were using a Lattice device, you'd use their JTAG component. In your ASIC, you can use whatever JTAG logic they offer. Regardless of the internal implementation, the top-level functionality is identical. Cheers, Dave
