JTAG boundary scan fails on dut with ArriaII GX FPGA

Hi,

this was the answer that I received:

From the symptoms that you describe, I believe it is likely that the anti-tamper bit is set on your FPGA. I guess that this was not on purpose. The functionality of the anti-tamper bit is dscribed in detail in AN556: http://www.altera.com/literature/an/an556.pdf but in short it disables all JTAG functionality except for the mandatory IEEE 1149.1 instructions (which does not include the ID).

You can verify whether or not this bit is set by checking the KEY_VERIFY register as described in AN556.

If you would like me to, I can send you a .jam file (i.e. STAPL format) which you can use to check the bit either with the Quartus II software or your own boundary scan tool. If you want me to do this, then please confirm the JTAG chain configuration for the chain which contains your Arria II FPGA.

The anti-tamper bit is set by an instruction which Altera does not publish, but I can tell you that it is one of the private instructions listed in the handbook ahpater on JTAG, volume 1, chapter 11, page 11-5: http://www.altera.com/literature/hb/arria-ii-gx/aiigx_51011.pdf

The most common ways for a private instruction to be accidentally sent are:

1) toggling TCK, TMS and TDI during diagnostic testing (e.g. by probing) and accidentally sending the code.

2) A timing violation which means that a code is incorrectly interpretted at the FPGA.