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晓郝's avatar
晓郝
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7 years ago

JESD204B RX is not locked to data

When I use Arria 10 JESD204B core to receive the data from four channels of AD6688, I find that rx_is_lockedtodata of two channels is always 0. The reference clock of transceiver remain deasserted un...
Nathan_R_Intel's avatar
Nathan_R_Intel
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7 years ago

​Arria 10 user guide clearly states that transceiver reference clock must be stable and free running at start of FPGA calibration. If this is not the case, the power up calibration could calibrate some of the CDR settings to values that cannot be cleared with user calibration. Hence, that's the reason you are facing the issue. Please make the transceiver reference clocks available at start of FPGA calibration to avoid the CDR cannot lock issue.

Regards,

Nathan

xytech's avatar
xytech
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7 years ago

Hi Nathan, @NathanR_Intel​

Your answer helps. Recently I am really struggling with this Calibration thing. From your words, can I say that if FPGA is not successfully calibrated / re-calibrated, XCVRs can still run, but may with lower performance than it should be?

If you are convenient, would you like to take a look a t this thread , some further description on my questions about A10 GX device calibration.

https://forums.intel.com/s/question/0D50P00004Gf0dgSAB/what-would-happen-if-transceiver-calibration-fails

Thanks, and happy weekend.